View AD7945_7592614.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

functional block diagrams v dd r fb dgnd ad7948 db7Cdb0 df/ dor ctrl ldac wr cslsb csmsb i out1 agnd v ref 12-bit dac 12 12 data override logic 12 dac register 12 input registers control logic data steering logic 8 cs wr v dd r fb i out1 agnd v ref dgnd db11Cdb0 AD7945 12-bit dac 12 input latch 12 ad7943 v dd r fb i out1 agnd i out2 sro stb1 dgnd stb2 stb3 stb4 clr ld1 ld2 sri v ref 12-bit dac dac register input shift register rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a +3.3 v/+5 v multiplying 12-bit dacs ad7943/AD7945/ad7948 features 12-bit multiplying dacs guaranteed specifications with +3.3 v/+5 v supply 0.5 lsbs inl and dnl low power: 5 m w typ fast interface 40 ns strobe pulsewidth (ad7943) 40 ns write pulsewidth (AD7945, ad7948) low glitch: 60 nv-s with amplifier connected fast settling: 600 ns to 0.01% with ad843 applications battery-powered instrumentation laptop computers upgrades for all 754x series dacs (5 v designs) general description the ad7943, AD7945 and ad7948 are fast 12-bit multiplying dacs that operate from a single +5 v supply (normal mode) and a single +3.3 v to +5 v supply (biased mode). the ad7943 has a serial interface, the AD7945 has a 12-bit parallel interface, and the ad7948 has an 8-bit byte interface. they will replace the industry-standard ad7543, ad7545 and ad7548 in many applications, and they offer superior speed and power consumption performance. the ad7943 is available in 16-lead dip, 16-lead sop (small outline package) and 20-lead ssop (shrink small outline package). the AD7945 is available in 20-lead dip, 20-lead sop and 20- lead ssop. the ad7948 is available in 20-lead dip, 20-lead sop and 20- lead ssop. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998
rev. b C2C ad7943/AD7945/ad7948Cspecifications 1 parameter b grades 2 t grade 2, 3 units test conditions/comments accuracy resolution 12 12 bits 1 lsb = v ref /2 12 = 2.44 mv when v ref =10v relative accuracy 0.5 0.5 lsb max differential nonlinearity 0.5 0.5 lsb max all grades guaranteed monotonic over temperature gain error t min to t max 2 2 lsb max gain temperature coefficient 4 2 2 ppm fsr/ c typ 5 5 ppm fsr/ c max output leakage current i out1 @ +25 c 10 10 na max see terminology section t min to t max 100 100 na max typically 20 na over temperature reference input input resistance 6 6 k w min typical input resistance = 9 k w 12 12 k w max digital inputs v inh , input high voltage 2.4 2.4 v min v inl , input low voltage 0.8 0.8 v max i inh , input current 1 1 m a max c in , input capacitance 4 10 10 pf max digital output (ad7943 sro) for 1 cmos load output low voltage (v ol ) 0.2 0.2 v max output high voltage (v oh )v dd C 0.2 v dd C 0.2 v min power requirements v dd range 4.5/5.5 4.5/5.5 v min/v max power supply sensitivity 4 d gain/ d v dd C75 C75 db typ i dd (ad7943) 5 5 m a max v inh = v dd C 0.1 v min, v inl = 0.1 v max. sro open circuit. no stb signal. typically 1 m a. typically 100 m a with a 1 mhz stb frequency. at input levels of 0.8 v and 2.4 v, i dd is typically 2.5 ma. i dd (AD7945, ad7948) 5 5 m a max v inh = v dd C 0.1 v min, v inl = 0.1 v max. typically 1 m a. at input levels of 0.8 v and 2.4 v, i dd is typically 2.5 ma. notes 1 the ad7943, AD7945 and ad7948 are specified in the normal current mode configuration and in the biased current mode for single- supply applications. figures 14 and 15 are examples of normal mode operation. 2 temperature ranges as follows: b grades: C40 c to +85 c; t grade: C55 c to +125 c. 3 the t grade applies to the AD7945 only. 4 guaranteed by design. specifications subject to change without notice. normal mode (ad7943: v dd = +4.5 v to +5.5 v; v iout1 = v iout2 = agnd = 0 v; v ref = +10 v; t a = t min to t max , unless otherwise noted. AD7945, ad7948: v dd = +4.5 v to +5.5 v; v iout1 = agnd = 0 v; v ref = +10 v; t a = t min to t max , unless otherwise noted.)
ad7943/AD7945/ad7948 rev. b C3C parameter a grades 2 units test conditions/comments accuracy resolution 12 bits 1 lsb = (v iout1 C v ref) /2 12 = 300 m v when v iout1 = 1.23 v and v ref = 0 v relative accuracy 1 lsb max differential nonlinearity 0.9 lsb max all grades guaranteed monotonic over temperature gain error @ +25 c 3 lsb max t min to t max 4 lsb max gain temperature coefficient 3 2 ppm fsr/ c typ 5 ppm fsr/ c max output leakage current see terminology section i out1 @ +25 c 10 na max t min to t max 100 na max typically 20 na over temperature input resistance this varies with dac input code @ i out2 pin (ad7943) 6 k w min @ agnd pin (AD7945, ad7948) 6 k w min digital inputs v inh , input high voltage @ v dd = +5 v 2.4 v min v inh , input high voltage @ v dd = +3.3 v 2.1 v min v inl , input low voltage @ v dd = +5 v 0.8 v max v inl , input low voltage @ v dd = +3.3 v 0.6 v max i inh , input current 1 m a max c in , input capacitance 3 10 pf max digital output (sro) for 1 cmos load output low voltage (v ol ) 0.2 v max output high voltage (v oh )v dd C 0.2 v min power requirements v dd range 3.0/5.5 v min/v max power supply sensitivity 3 d gain/ d v dd C75 db typ i dd (ad7943) 5 m a max v inh = v dd C 0.1 v min, v inl = 0.1 v max. sro open circuit; no stb signal; typically 1 m a. typically 100 m a with 1 mhz stb frequency. i dd (AD7945, ad7948) 5 m a max v inh = v dd C 0.1 v min, v inl = 0.1 v max. typically 1 m a. notes 1 these specifications apply with the devices biased up at 1.23 v for single supply applications. the model numbering reflects t his by means of a Cb suffix (for example: ad7943an-b). figure 16 is an example of biased mode operation. 2 temperature ranges as follows: a versions: C40 c to +85 c. 3 guaranteed by design. specifications subject to change without notice. biased mode specifications 1 (ad7943: v dd = +3 v to +5.5 v; v iout1 =v iout2 = agnd = 1.23 v; v ref = +0 v to 2.45 v; t a = t min to t max , unless other- wise noted. AD7945, ad7948: v dd = +3 v to +5.5 v; v iout1 = agnd = 1.23 v; v ref = +0 v to 2.45 v; t a = t min to t max , unless otherwise noted.)
ad7943/AD7945/ad7948 rev. b C4C ac performance characteristics normal mode parameter b grades t grade units test conditions/comments dynamic performance output voltage settling time 600 700 ns typ to 0.01% of full-scale range. v ref = +10 v; dac latch alternately loaded with all 0s and all 1s digital to analog glitch impulse 60 60 nv-s typ measured with v ref = 0 v. dac latch alternately loaded with all 0s and all 1s multiplying feedthrough error C75 C75 db max dac latch loaded with all 0s output capacitance 60 60 pf max all 1s loaded to dac 30 30 pf max all 0s loaded to dac digital feedthrough (ad7943) 5 5 nv-s typ feedthrough to the dac output with ld1 , ld2 high and alternate loading of all 0s and all 1s into the input shift register digital feedthrough (AD7945, ad7948) 5 5 nv-s typ feedthrough to the dac output with cs high and alternate loading of all 0s and all 1s to the dac bus total harmonic distortion C83 C83 db typ output noise spectral density @ 1 khz 35 35 nv/ ? hz typ all 1s loaded to dac. v ref = 0 v. output op amp is op07 specifications subject to change without notice. (ad7943: v dd = +4.5 v to +5.5 v; v iout1 = v iout2 = agnd = 0 v. AD7945, ad7948: v dd = +4.5 v to +5.5 v; v iout1 =agnd = 0 v. v ref = 6 v rms, 1 khz sine wave; t a = t min to t max ; dac output op amp is ad843; unless otherwise noted.) these characteristics are in- cluded for design guidance and are not subject to test. ac performance characteristics biased mode (ad7943: v dd = +3 v to +5.5 v; v iout1 = v iout2 = agnd = 1.23 v. AD7945, ad7948: v dd = +3 v to +5.5 v; v iout1 = agnd = 1.23 v. v ref = 1 khz, 2.45 v p-p, sine wave biased at 1.23 v; dac output op amp is ad820; t a = t min to t max ; unless otherwise noted.) these characteristics are included for design guidance and are not subject to test. parameter a grades units test conditions/comments dynamic performance output voltage settling time 5 m s typ to 0.01% of full-scale range. v ref = 0 v dac latch alternately loaded with all 0s and all 1s digital to analog glitch impulse 60 nv-s typ v ref = 1.23 v. dac register alternately loaded with all 0s and all 1s multiplying feedthrough error C75 db max dac latch loaded with all 0s output capacitance 60 pf max all 1s loaded to dac 30 pf max all 0s loaded to dac digital feedthrough 5 nv-s typ feedthrough to the dac output with ld1 , ld2 high and alternate loading of all 0s and all 1s into the input shift register digital feedthrough (AD7945, ad7948) 5 nv-s typ feedthrough to the dac output with cs high and alternate loading of all 0s and all 1s to the dac bus total harmonic distortion C83 db typ output noise spectral density @ 1 khz 25 nv/ ? hz typ all 1s loaded to dac. v ref = 1.23 v specifications subject to change without notice.
ad7943/AD7945/ad7948 rev. b C5C (t a = t min to t max , unless otherwise noted) limit @ limit @ parameter v dd = +3 v to +3.6 v v dd = +4.5 v to +5.5 v units description t stb 2 60 40 ns min stb pulsewidth t ds 15 10 ns min data setup time t dh 35 25 ns min data hold time t sri 55 35 ns min sri data pulsewidth t ld 55 35 ns min load pulsewidth t clr 55 35 ns min clr pulsewidth t asb 0 0 ns min min time between strobing input shift register and loading dac register t sv 3 60 35 ns max stb clocking edge to sro data valid delay notes 1 all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. tr and tf sho uld not exceed 1 m s on any digital input. 2 stb mark/space ratio range is 60/40 to 40/60. 3 t sv is measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.8 v or 2.4 v. specifications subject to change without notice. t stb stb1, stb2, stb4 stb3 t ds t dh t sri sri db11(n) (msb) db10(n) db0(n) db0(nC1) db10(nC1) ld1 , ld2 , clr sro t sv t ld , t clr t asb figure 1. ad7943 timing diagram to output pin c l 50pf 1.6ma i ol +2.1v i oh 200 m a figure 2. load circuit for digital output timing specifications ad7943 timing specifications 1
ad7943/AD7945/ad7948 rev. b C6C AD7945 timing specifications 1 (t a = t min to t max , unless otherwise noted) limit @ limit @ parameter v dd = +3 v to +3.6 v v dd = +4.5 v to +5.5 v units description t ds 35 20 ns min data setup time t dh 10 10 ns min data hold time t cs 60 40 ns min chip select setup time t ch 0 0 ns min chip select hold time t wr 60 40 ns min write pulsewidth notes 1 all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. specifications subject to change without notice. data valid cs t ch t ds t dh wr db11Cdb0 t cs t wr figure 3. AD7945 timing diagram ad7948 timing specifications 1 (t a = t min to t max , unless otherwise noted) limit @ limit @ parameter v dd = +3 v to +3.6 v v dd = +4.5 v to +5.5 v units description t ds 45 30 ns min data setup time t dh 10 10 ns min data hold time t cws 0 0 ns min csmsb or cslsb to wr setup time t cwh 0 0 ns min csmsb or cslsb to wr hold time t lws 0 0 ns min ldac to wr setup time t lwh 0 0 ns min ldac to wr hold time t wr 60 40 ns min write pulsewidth notes 1 all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. specifications subject to change without notice. data valid data valid wr t cws t cwh t cws t cwh t lwh t lws t dh t ds t wr t wr t dh t ds csmsb cslsb ldac db7Cdb0 figure 4. ad7948 timing diagram
ad7943/AD7945/ad7948 rev. b C7C ordering guide temperature linearity nominal package model range error (lsbs) supply voltage option 1 ad7943bn C40 c to +85 c 0.5 +5 v n-16 ad7943br C40 c to +85 c 0.5 +5 v r-16 ad7943brs C40 c to +85 c 0.5 +5 v rs-20 ad7943an-b C40 c to +85 c 1 +3.3 v to +5 v n-16 ad7943ars-b C40 c to +85 c 1 +3.3 v to +5 v rs-20 AD7945bn C40 c to +85 c 0.5 +5 v n-20 AD7945br C40 c to +85 c 0.5 +5 v r-20 AD7945brs C40 c to +85 c 0.5 +5 v rs-20 AD7945an-b C40 c to +85 c 1 +3.3 v to +5 v n-20 AD7945ars-b C40 c to +85 c 1 +3.3 v to +5 v rs-20 AD7945tq C55 c to +125 c 1 +5 v q-20 ad7948bn C40 c to +85 c 0.5 +5 v n-20 ad7948br C40 c to +85 c 0.5 +5 v r-20 ad7948brs C40 c to +85 c 0.5 +5 v rs-20 ad7948an-b C40 c to +85 c 1 +3.3 v to +5 v n-20 ad7948ars-b C40 c to +85 c 1 +3.3 v to +5 v rs-20 note 1 n = plastic dip; r = sop (small outline package); rs = ssop (shrink small outline package); q = cerdip. absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . .C0.3 v to +6 v i out1 to dgnd . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v i out2 to dgnd . . . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . . C0.3 v to v dd + 0.3 v v rfb , v ref to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . 15 v input current to any pin except supplies 2 . . . . . . . . 10 ma operating temperature range industrial (a, b versions) . . . . . . . . . . . . . C40 c to +85 c extended (t version) . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c dip package, power dissipation . . . . . . . . . . . . . . . . 670 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 116 c/w lead temperature, soldering, (10 sec) . . . . . . . . . . +260 c sop package, power dissipation . . . . . . . . . . . . . . . . . 450 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c ssop package, power dissipation . . . . . . . . . . . . . . . . 875 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 132 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7943/AD7945/ad7948 feature proprietary esd protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad7943/AD7945/ad7948 rev. b C8C terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero error and full-scale error and is normally expressed in least significant bits or as a percentage of full- scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. gain error gain error is a measure of the output error between an ideal dac and the actual device output. it is measured with all 1s in the dac after offset error has been adjusted out and is ex- pressed in least significant bits. gain error is adjustable to zero with an external potentiometer. output leakage current output leakage current is current which flows in the dac lad- der switches when these are turned off. for the i out1 terminal, it can be measured by loading all 0s to the dac and measuring the i out1 current. minimum current will flow in the i out2 line when the dac is loaded with all 1s. output capacitance this is the capacitance from the i out1 pin to agnd. output voltage settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. for these devices, it is specified both with the ad843 as the output op amp in the normal current mode and with the ad820 in the biased current mode. digital to analog glitch impulse this is the amount of charge injected into the analog output when the inputs change state. it is specified as the area of the glitch in nv-s. it is measured with the reference input connected to agnd and the digital inputs toggled between all 1s and all 0s. as with settling time, it is specified with both the ad817 and the ad820. ac feedthrough error this is the error due to capacitive feedthrough from the dac reference input to the dac i out1 terminal, when all 0s are loaded in the dac. digital feedthrough when the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the i out1 pin and subsequently on the op amp output. this noise is digital feedthrough. pin configurations dip/sop ssop dip/sop/ssop dip/sop/ssop 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 top view (not to scale) AD7945 db5 db6 db7 agnd dgnd db11 db8 db9 db10 db4 db3 db2 v ref v dd wr db1 db0 cs i out1 r fb top view (not to scale) ad7943 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 i out1 i out2 agnd stb1 ld1 sro sri stb2 r fb v ref v dd clr dgnd stb4 stb3 ld2 top view (not to scale) ad7943 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 nc = no connect stb2 sri sro i out2 agnd stb1 ld1 nc nc ld2 stb3 stb4 v ref v dd clr dgnd nc nc i out1 r fb top view (not to scale) ad7948 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 db4 db5 db6 agnd dgnd csmsb db7 (msb) ctrl df/ dor db3 db2 db1 v ref v dd wr db0 (lsb) ldac cslsb i out1 r fb
ad7943/AD7945/ad7948 rev. b C9C ad7943 pin function descriptions pin mnemonic description i out1 dac current output terminal 1. i out2 dac current output terminal 2. this should be connected to the agnd pin. agnd this pin connects to the back gates of the current steering switches. in normal operation, it should be connected to the signal ground of the system. in biased single-supply operation it may be biased to some voltage between 0 v and the 1.23 v. see figure 11 for more details. stb1 this is the strobe 1 input. data is clocked into the input shift register on the rising edge of this signal. stb3 must be high. stb2, stb4 must be low. ld1 , ld2 active low inputs. when both of these are low, the dac register is updated and the output will change to reflect this. sri serial data input. data on this line will be clocked into the input shift register on one of the strobe inputs, when they are enabled. stb2 this is the strobe 2 input. data is clocked into the input shift register on the rising edge of this signal. stb3 must be high. stb1, stb4 must be low. stb3 this is the strobe 3 input. data is clocked into the input shift register on the falling edge of this signal. stb1, stb2, stb4, must be low. stb4 this is the strobe 4 input. data is clocked into the input shift register on the rising edge of this signal. stb3 must be high. stb1, stb2 must be low. dgnd digital ground. clr asynchronous clr input. when this input is taken low, all 0s are loaded to the dac latch. v dd power supply input. this is nominally +5 v for normal mode operation and +3.3 v to +5 v for biased mode operation. v ref dac reference input. r fb dac feedback resistor pin. AD7945 pin function descriptions pin mnemonic description i out1 dac current output terminal 1. agnd this pin connects to the back gates of the current steering switches. the dac i out2 terminal is also connected internally to this point. dgnd digital ground. db11Cdb0 digital data inputs. cs active low, chip select input. wr active low, write input. v dd power supply input. this is nominally +5 v for normal mode operation and +3.3 v to +5 v for biased mode operation. v ref dac reference input. r fb dac feedback resistor pin.
ad7943/AD7945/ad7948 rev. b C10C ad7948 pin function descriptions pin mnemonic description i out1 dac current output terminal 1. normally terminated at the virtual ground of output amplifier. agnd analog ground pin. this pin connects to the back gates of the current steering switches. the dac i out2 terminal is also connected internally to this point. dgnd digital ground pin. csmsb chip select most significant byte. active low input. used in combination with wr to load external data into the input register or in combination with ldac and wr to load external data into both input and dac registers. df/ dor data format/data override. when this input is low, data in the dac register is forced to one of two override codes selected by ctrl. when the override signal is removed, the dac output returns to reflect the value in the dac register. with df/ dor high, ctrl selects either a left or right justified input data format. for normal operation, df/ dor is held high. see table i. ctrl control input. see df/ dor description. db7Cdb0 digital data inputs. ldac load dac input, active low. this signal, in combination with others, is used to load the dac register from either the input register or the external data bus. cslsb chip select least significant (ls) byte. active low input. used in combination with wr to load external data into the input register or in combination with wr and ldac to load external data into both input and dac registers. wr write input, active low. this active low signal, in combination with others is used in loading external data into the ad7948 input register and in transferring data from the input register to the dac register. v dd power supply input. this is nominally +5 v for normal mode operation and +3.3 v to +5 v for biased mode operation. v ref dac reference input. r fb dac feedback resistor pin. table ii. truth table for ad7948 write operation wr csmsb cslsb ldac function 0 1 0 1 load ls byte to input register 0 1 0 0 load ls byte to input register and dac register 0 0 1 1 load ms byte to input register 0 0 1 0 load ms byte to input register and dac register 0 1 1 0 load input register to dac register 1 x x x no data transfer table i. truth table for df/ dor ctrl df/ dor ctrl function 0 0 dac register contents overridden by all 0s 0 1 dac register contents overridden by all 1s 1 0 left-justified input data selected 1 1 right-justified input data selected
ad7943/AD7945/ad7948 rev. b C11C typical performance curves v ref C volts 0.5 0.4 0 210 4 dnl C lsb s 68 0.3 0.2 0.1 v dd = +5v t a = +25 8 c op amp = ad843 figure 5. differential nonlinearity error vs. v ref (normal mode) v ref C volts 1.0 0.9 0 210 468 0.6 0.3 0.2 0.1 0.8 0.7 0.4 0.5 inl C lsb s v dd = +5v t a = +25 8 c op amp = ad843 figure 6. integral nonlinearity error vs. v ref (normal mode) input code 0.50 0.25 C0.50 0 4095 1024 linearity error C lsb s 2048 3072 0.00 C0.25 v dd = +5v v ref = +10v op amp = ad843 t a = +25 8 c figure 7. all codes linearity in normal mode (v dd = +5 v) |v ref C v bias | C volts 6 0 0.2 1.4 0.4 inl, dnl C lsb s 0.6 0.8 1.0 1.2 5 4 3 2 1 v dd = +3.3v t a = +25 8 c op amp = ad820 figure 8. linearity error vs. v ref (biased mode)
ad7943/AD7945/ad7948 rev. b C12C input code 1.00 0.50 C1.00 0 4095 1024 linearity error C lsb s 2048 3072 0.00 C0.50 v dd = +3.3v v ref = 0v v bias = 1.23v op amp = ad820 t a = +25 8 c figure 9. all codes linearity in biased mode (v dd = +3.3 v) frequercy C hz C50 C55 C100 100 100k 1k thd C dbs 10k C80 C85 C90 C95 C70 C75 C60 C65 v dd = +5v t a = +25 8 c v in = 6v rms op amp = ad711 figure 10. total harmonic distortion vs. frequency 10 0% 100 90 200ns 5v 200ns 50mv v dd = +5v t a = +25 8 c v ref = 0v op amp = ad711 ad711 output figure 11. digital-to-analog glitch impulse frequency C hz 0 C10 C100 1k 10m 10k 100k 1m C40 C70 C80 C90 C20 C30 C60 C50 v dd = +5v t a = +25 8 c v in = 20v p-p op amp = ad711 dac loaded with all 0 s dac loaded with all 1 s figure 12. multiplying frequency response vs. digital code
ad7943/AD7945/ad7948 rev. b C13C general description d/a section the ad7943, AD7945 and ad7948 are 12-bit current-output d/a converters. a simplified circuit diagram is shown in fig- ure 13. the dac architecture is segmented. this means that the 2 msbs of the 12-bit data word are decoded to drive the three switches a, b and c. the remaining 10 bits of the data word drive the switches s0 to s9 in a standard inverting r-2r ladder configuration. each of the switches a to c steers 1/4 of the total reference current into either i out1 or i out2 with the remaining 1/4 of the total current passing through the r-2r section. switches s9 to s0 steer binarily weighted currents into either i out1 or i out2 . if i out1 and i out2 are kept at the same potential, a constant cur- rent flows in each ladder leg, regardless of digital input code. thus, the input resistance seen at v ref is always constant. it is equal to r/2. the v ref input may be driven by any reference voltage or current, ac or dc that is within the absolute maxi- mum ratings. the device provides access to the v ref , r fb , and i out1 termi- nals of the dac. this makes the device extremely versatile and allows it to be configured in several different operating modes. examples of these are shown in the following sections. the ad7943 also has a separate i out2 pin. in the AD7945 and ad7948 this is internally tied to agnd. when an output amplifier is connected in the standard configu- ration of figure 14, the output voltage is given by: v out = Cd v ref where d is the fractional representation of the digital word loaded to the dac. d can be set from 0 to 4095/4096, since it has 12-bit resolution. v ref 2r r/2 rr r ca bs9s8s0 r fb i out1 i out2 2r 2r 2r 2r 2r 2r shown for all 1 s on dac figure 13. simplified d/a circuit diagram unipolar binary operation (two-quadrant multiplication) figure 14 shows the standard unipolar binary connection dia- gram for the ad7943, AD7945 and ad7948. when v in is an ac signal, the circuit performs two-quadrant multiplication. resistors r1 and r2 allow the user to adjust the dac gain error. with a specified gain error of 2 lsbs over temperature, these are not necessary in many applications. circuit offset is due completely to the output amplifier offset. it can be re- moved by adjusting the amplifier offset voltage. alternatively, choosing a low offset amplifier makes this unnecessary. a1 should be chosen to suit the application. for example, the op07 is ideal for very low bandwidth applications (10 khz or i out1 i out2 a1 v out signal ground a1: op07 ad711 ad843 ad845 agnd dac v ref r1 20 v ad7943/45/48 v in r2 10 v rfb c1 notes 1. only one dac is shown for clairity. 2. digital input connections are omitted. 3. c1 phase compensation (5 C 15pf) may be required when using high speed amplifier. figure 14. unipolar binary operation lower) while the ad711 is suitable for medium bandwidth ap- plications (200 khz or lower). for high bandwidth applications of greater than 200 khz, the ad843 and ad847 offer very fast settling times. the code table for figure 14 is shown in table iii. table iii. unipolar binary code digital input analog output msb lsb (v out as shown in figure 14) 1111 1111 1111 Cv ref (4095/4096) 1000 0000 0001 Cv ref (2049/4096) 1000 0000 0000 Cv ref (2048/4096) 0111 1111 1111 Cv ref (2047/4096) 0000 0000 0001 Cv ref (1/4096) 0000 0000 0000 Cv ref (0/4096) = 0 note nominal lsb size for the circuit of figure 14 is given by: v ref (1/4096).
ad7943/AD7945/ad7948 rev. b C14C bipolar operation (four-quadrant multiplication) figure 15 shows the standard connection diagram for bipolar operation of the ad7943, AD7945 and ad7948. the coding is offset binary as shown in table iv. when v in is an ac signal, the circuit performs four-quadrant multiplication. resistors r1 and r2 are for gain error adjustment and are not needed in many applications where the device gain error specifications are adequate. to maintain the gain error specifications, resistors r3, r4 and r5 should be ratio matched to 0.01%. i out1 i out2 a1 v out signal ground agnd dac v ref r1 20 v ad7943/45/48 v in r2 10 v rfb c1 r4 20k v a2 10k v 20k v r3 r5 notes 1. only one dac is shown for clairity. 2. digital input connections are omitted. 3. c1 phase compensation (5 C 15pf) may be required when using high speed amplifier, a1. figure 15. bipolar operation (four-quadrant multiplication) suitable dual amplifiers for use with figure 15 are the op270 (low noise, low bandwidth, 15 khz), the ad712 (medium bandwidth, 200 khz) or the ad827 (wide bandwidth, 1 mhz). table iv. bipolar (offset binary) code table digital input analog output msb lsb (v out as shown in figure 15) 1111 1111 1111 +v ref (2047/2048) 1000 0000 0001 +v ref (1/2048) 1000 0000 0000 +v ref (0/2048) = 0 0111 1111 1111 Cv ref (1/2048) 0000 0000 0001 Cv ref (2047/2048) 0000 0000 0000 Cv ref (2048/2048) = Cv ref note nominal lsb size for the circuit of figure 15 is given by: v ref (1/2048). single supply applications the -b versions of the devices are specified and tested for single supply applications. figure 16 shows the recommended circuit for operation with a single +5 v to +3.3 v supply. the i out2 and agnd terminals are biased to 1.23 v. thus, with 0 v applied to the v ref terminal, the output will go from 1.23 v (all 0s loaded to the dac) to 2.46 v (all 1s loaded). with 2.45 v applied to the v ref terminal, the output will go from 1.23 v (all 0s loaded) to 0.01 v (all 1s loaded). it is important when con- sidering inl in a single-supply system to realize that most single-supply amplifiers cannot sink current and maintain zero volts at the output. in figure 16, with v ref = 2.45 v the re- quired sink current is 200 m a. the minimum output voltage level is 10 mv. op amps like the op295 are capable of main- taining this level while sinking 200 m a. figure 16 shows the i out2 and agnd terminals being driven by an amplifier. this is to maintain the bias voltage at 1.23 v as the impedance seen looking into the i out2 terminal changes. this impedance is code dependent and varies from infinity (all 0s loaded in the dac) to about 6 k w minimum. the ad589 has a typical output resistance of 0.6 w and it can be used to drive the terminals directly. however, this will cause a typical linearity degradation of 0.2 lsbs. if this is unacceptable then the buffer amplifier is necessary. figure 9 shows the typical linearity performance of the ad7943/AD7945/ad7948 when used as in figure 16 with v dd set at +3.3 v and v ref = 0 v. i out1 i out2 a1 v out signal ground a1: op295 ad822 op283 agnd dac v ref ad7943/45/48 v in rfb c1 a1 +5v 5.6k v ad589 +3.3v v dd dgnd figure 16. single supply system
ad7943/AD7945/ad7948 rev. b C15C microprocessor interfacing ad7943 to adsp-2101 interface figure 17 shows the ad7943 to adsp-2101 interface diagram. the dsp is set up for alternate inverted framing with an inter- nally generated sclk. tfs from the adsp-2101 drives the stb1 input on the ad7943. the serial word length should be set at 12. this is done by making slen = 11 (1011 binary). the slen field is bits 3C0 in the sport control register (0x3ff6 for sport0 and 0x3ff2 for sport1). with the 16 mhz version of the adsp-2101, the maximum output sclk is 8 mhz. the ad7943 setup and hold time of 10 ns and 25 ns mean that it is compatible with the dsp when running at this speed. the output flag drives both ld1 and ld2 and is brought low to update the dac register and change the analog output. adsp-2101 ad7943 stb4 stb2 +5v tfs sclk dt output flag clr stb3 ld1 ld2 stb1 sri figure 17. ad7943 to adsp-2101 interface ad7943 to dsp56001 interface figure 18 shows the interface diagram for the ad7943 to the dsp56001. the dsp56001 is configured for normal mode synchronous operation with gated clock. the serial clock, sck, is set up as an output from the dsp and the serial word length is set for 12 bits (wl0 = 1, wl1 = 0, in control register a). sck from the dsp56001 is applied to the ad7943 stb3 in- put. data from the dsp56000 is valid on the falling edge of sck and this is the edge which clocks the data into the ad7943 shift register. stb1, stb2 and stb4 are tied low on the ad7943 to permanently enable the stb3 input. when the 12-bit serial word has been written to the ad7943, the ld1 , ld2 inputs are brought low to update the dac register. dsp56001 ad7943 stb4 stb2 stb1 +5v sck std output flag clr stb3 ld1 ld2 sri figure 18. ad7943 to dsp56001 interface AD7945 to mc68000 interface figure 19 shows the mc68000 interface to the AD7945. the appropriate data is written into the dac in one move instruc- tion to the appropriate memory location. mc68000 address decode AD7945 cs wr db11 C db0 a1 C a23 as dtack r/ w d15 C d0 figure 19. AD7945 to mc68000 interface ad7948 to z80 interface figure 20 is the interface between the ad7948 and the 8-bit bus of the z80 processor. three write operations are needed to load the dac. the first two load the ms byte and the ls byte and the third brings the ldac low to update the output. z80 address decode ad7948 csmsb wr db7 C db0 a0 C a15 mreq wr d7 C d0 cslsb ldac address bus data bus figure 20. ad7948 to z80 interface
ad7943/AD7945/ad7948 rev. b C16C printed in u.s.a. c1901bC0C5/98 outline dimensions dimensions shown in inches and (mm). 16-lead plastic dip (n-16) 16 18 9 0.840 (21.34) 0.745 (18.92) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.26) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead plastic dip (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead sop (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc

▲Up To Search▲

Price & Availability of AD7945

	To Download AD7945 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .